Browse Prior Art Database

Interface Between Two Transmission Lines Having Different Transmission Speeds

IP.com Disclosure Number: IPCOM000081162D
Original Publication Date: 1974-Apr-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Poulet, A: AUTHOR

Abstract

The present system enables the transmission of digital information between two networks having different transmission speeds, and uses this difference to transmit control signals.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 47% of the total text.

Page 1 of 3

Interface Between Two Transmission Lines Having Different Transmission Speeds

The present system enables the transmission of digital information between two networks having different transmission speeds, and uses this difference to transmit control signals.

According to the operating mode of the system, a specific bit pattern called "forbidden pattern" is stated as being unacceptable and normally the bit stream is processed to avoid the occurrence of such a pattern. This allows the use of the pattern as a flag for indicating the presence, in the high-speed bit stream, of a group of a predetermined number of hits which are not a part of the information bit stream and have a specific significance. Thus, an "additional bit set" is formed by the forbidden pattern, followed by the group of bits indicating a status through the combination of their values; it is possible that these bits have a value combination indicating "no significance", this resulting in that the additional bit set forms a set of idle bits which are used only to compensate for the difference of transmission speed.

Without any limiting intention, it is assumed in the description that one of the transmission networks has a rate of 1200 information elements per second, the second one has a rate of 1800 information elements per second, that the information element is a binary element, and that the forbidden pattern is formed by five consecutive 0's.

The interface, enabling the exchange of information, comprises a first part 1 enabling the transfer of information from the low-speed line to the higher speed line, and a second part 10 enabling the reciprocal information transfer. Modems MOD 1 and MOD 2 enable information transmission and reception on respective networks NW1 and NW2.

In input circuits 2, the data on line L are registered through OR circuit 01 in trigger T0, under the control of clock pulses CL 1200 passing through OR circuits
02. The 0 values on L are counted by counter C01 through AND circuit A2. Each time the count reaches 4, C01 delivers a high level which operates as a forced 1 on the input of trigger T0 through OR circuit 01 and through OR circuits 02, as a pulse causing trigger T0 to register the forced value 1. At the occurrence of any 1 at the T0 input, counter C01 is reset through AND circuit A1. All the clock pulses delivered by OR circuit 02 are sent on line CL1 to control circuits 9.

Control circuits 9 normally transfer (switch SW in position R) the information signals from trigger TO on line DAL and the clock pulses on line CL1, to registering circuits 3. When SW is in position A, circuits 9 insert the "additional bit set" in the data stream entering circuits 3, this being done under the control of specific clock pulses CL. The input rate of the bits entering circuits 3 is essentially variable; the normal rate of 1200 bits/sec is slightly modified when a 1 is forced by circuits 2, or is strongly modified when an "additional bit set" is forced by...