Browse Prior Art Database

Design Verification and Defect Detection

IP.com Disclosure Number: IPCOM000081183D
Original Publication Date: 1974-Apr-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Kuney, JS: AUTHOR

Abstract

Described is a technique which enables the design integrity and quality of a glass mask used in semiconductor photolithographic processing to be checked and verified, prior to the processing of the semiconductor wafers and their final testing.

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Design Verification and Defect Detection

Described is a technique which enables the design integrity and quality of a glass mask used in semiconductor photolithographic processing to be checked and verified, prior to the processing of the semiconductor wafers and their final testing.

Previously, original design information in digital data form (GL-1) was plotted and was compared to post processed plotted data, by manually aligning shapes on a light table. Such comparison was difficult and prone to error, but it did ensure to some degree that the post-processed data used to drive a Mann single-segment mask generator was the same as the original design information, and had not been distorted in passing through the post processor, wherein software manipulated the data to put it in proper form for driving the mask generator.

In the new scheme, as diagrammed, the original data is passed through the post processor twice to obtain two sets of post processed data PP1 and PP2. Each set of data PP1 and PP2 is used on the pattern generator to generate a single-segment mask SS1 or SS2. A positive and a negative photoprint is now made of each single-segment mask SS1 and SS2 to provide SS1P, SS1N, SS2P and SS2N masks. Now the SS1P and SS2N masks are aligned in close proximity and similarly the SS1N and SS2P masks are closely aligned. Both mask pairs are now inspected to determine if light will pass through any part of them.

If light can be detected, an error has been found. Th...