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Width To Length Ratio Design Program for Interfacing Static FET Circuits

IP.com Disclosure Number: IPCOM000081189D
Original Publication Date: 1974-Apr-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 62K

Publishing Venue

IBM

Related People

Love, RD: AUTHOR [+2]

Abstract

This program designs width-to-length ratios for active and load devices of static field-effect transistor (FET) circuits, prior to their formation in a semiconductor. An iterative process combines physical models of interacting static FET circuits to meet a required size, power, or performance specification. Each circuit is electrically characterized by an output rise time, an output fall time and an associated delay time. The input load capacitance of each circuit is calculated by the program.

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Width To Length Ratio Design Program for Interfacing Static FET Circuits

This program designs width-to-length ratios for active and load devices of static field-effect transistor (FET) circuits, prior to their formation in a semiconductor. An iterative process combines physical models of interacting static FET circuits to meet a required size, power, or performance specification. Each circuit is electrically characterized by an output rise time, an output fall time and an associated delay time. The input load capacitance of each circuit is calculated by the program.

A simplified flow diagram of the auto gate select (AGS) algorithm is shown in the figure. The algorithm follows an iterative procedure. To produce a solution to specified circuit design constraints, AGS computations converge to a solution,
i.e., a set of device sizes which satisfy design constraints and provide a stable AC design.

At an operation 10 the program is initialized by inputting the following data for each circuit in each net:
a) Rise Time (TRI) and Fall Time (TFI) - an initial

approximation of circuit output rise and fall

time. The approximation is chosen to be the same for

each circuit under analysis. A good approximation

of TRI and TFI decreases the number of iterations

required to converge to a solution.
b) Load capacitance is calculated by the circuit designer or

by a program.
c) Ground resistance of each circuit is entered.
d) A master logic list, describing input and output

connections for each circuit, is entered.
e) A specification type is designated for each circuit.

Circuit type

may be designed to be of a fixed power requirement,

a fixed size requirement, or fixed delay performance.
f) Minimum stepping increment is entered for increasing and

rounding up circuit power.
g) Maximum number of program iterations before terminating is

entered.
h) Maximum power specification for each circuit is entered.

The specification guarantees convergence of the program.
i) A truncation constant is specified. The constant indicates

the minimum change in rise

and fall times. When the constant is not

exceeded by any circuit, the program interprets the

condition as convergence and terminates further circuit

design calculations.

At an operation 20 the program enters storage and selects a net (I) to be analyzed. In a decision 30 the program determines the specification type for analysis.

1

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For the case of a delay specification an operation 40 calculates power as a function of driving circuits input waveforms (TRI and TFI), the load (CL) in picofarads, the active device size (WLA) and the required delay in nanoseco...