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First Generation Bifrequency Pyramdic Pulse Generator

IP.com Disclosure Number: IPCOM000081203D
Original Publication Date: 1974-Apr-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Related People

Blair, HH: AUTHOR [+2]

Abstract

In the measurement of time delay of signals on a communication line, it is seldom necessary to measure an actual delay, but it is important to determine if the relative delay between a base frequency and a test frequency is within acceptable limits.

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First Generation Bifrequency Pyramdic Pulse Generator

In the measurement of time delay of signals on a communication line, it is seldom necessary to measure an actual delay, but it is important to determine if the relative delay between a base frequency and a test frequency is within acceptable limits.

The relative delay can be easily observed if a signal of the type shown in Fig. 1 is sent across the line and observed after transmission. The signal will consist of a number of cycles of a base frequency. here shown as 1800 hertz, followed by a pause equal to an acceptable time delay plus 10% for the test frequency, then a fixed number of cycles of the test frequency followed by another pause of the same length, and ending with another burst of the base frequency followed by a third pause. Observation of the relative widths of the two pauses will indicate the relative delay of the test frequency, as compared to the base frequency. Transmission of a number of such signals with different test frequencies, will indicate if the communication line is within

The structure for generating the test waveform is diagrammed in Fig. 2. The sine-wave generation is controlled by a ring counter 1 of the type in which, starting from one end, the stages are successively turned on by input pulses until all stages are on, and then starts turning the stages off from the same end until all stages are off, and then repeating the cycle as long as desired. A voltage divider 2, composed of a series of adjustable resistances 5 and a terminating resistor 6 is connected between the terminals 7 of a voltage supply, and has the junction between the last resistor 5 and resistor 6 connected through a low-pass filter 8 to an output terminal 9.

The signal on terminal 9 may be directly connected to a transmission, but is preferably recorded for wider use. Each resistor 5 is shunted by a switch controlled by a corresponding stage of the ring 1 so that the resistances 5 are successively shorted out of the voltage divider, and then successively cut back into the circuit as counter ring 1 goes through its cycle. By proper adjustment of resistances 5, any stepwise waveform, preferably approximately sinusoidal can be generated at the voltage divider junction to give a smooth wave output after filter 8. The frequency of cycling of ring 1 is controlled by two adjustable clocks 10 and 11, one of which is selected by a flip-flop 12 to dr...