Browse Prior Art Database

Computer With Stoppable Oscillator

IP.com Disclosure Number: IPCOM000081232D
Original Publication Date: 1974-Apr-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Brandon, M: AUTHOR

Abstract

A small computer designed for equipment testing is driven by a conventional oscillator 1. The oscillator is stopped by any negative signals into an OR circuit 2. Inverter 3 and AND circuit 4 ensure that the oscillator stops when point 5 is high. When the signals are raised, the oscillator restarts.

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Computer With Stoppable Oscillator

A small computer designed for equipment testing is driven by a conventional oscillator 1. The oscillator is stopped by any negative signals into an OR circuit
2. Inverter 3 and AND circuit 4 ensure that the oscillator stops when point 5 is high. When the signals are raised, the oscillator restarts.

SAC STOP: Storage access control (SAC) stop is generated to synchronize the computer and I/O. Fig. 2(a) shows SAC STOP on input. ICMD is dropped by the computer and is answered by DG from the I/O device. SAC STOP is signalled for the duration of DG. Fig. 2(b) shows SAC STOP on output. SAC STOP is generated when DR is signalled by the computer and is raised when the rise of response DC is received.

ESTOR WT: Extension storage is slower than main store. The oscillator is stopped during the difference in cycle time between main store and extension storage.

The oscillator can also be stopped during initial program load.

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