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Browse Prior Art Database

Electrostatic Wafer Flattener

IP.com Disclosure Number: IPCOM000081261D
Original Publication Date: 1974-Apr-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Wardly, GA: AUTHOR

Abstract

A structure is provided for supporting a thin semiconductor wafer, i.e., silicon, in an evacuated chamber, while the top surface of the wafer is being conformed to a predetermined surface pattern.

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Electrostatic Wafer Flattener

A structure is provided for supporting a thin semiconductor wafer, i.e., silicon, in an evacuated chamber, while the top surface of the wafer is being conformed to a predetermined surface pattern.

In the figure, an electrically conductive silicon wafer 2 rests on an insulating film, for example, mica or MYLAR* 4. This insulating film in turn rests upon a metal foil 10, having an area substantially equal to the silicon 2 area, which is supported by an electrically conductive ring 12. The top surface of the insulating film 4 has partial metallization 6 Which is electrically grounded, and is forced to contact the edge of the silicon wafer 2 by the compression produced between the clamp 8 and the ring 12. A supply voltage, not shown, applies a voltage to the foil 10 through conductors 14, causing an electrostatic attraction between the foil in and the silicon wafer 2.

Above the silicon wafer 2 are a plurality of sensors 16, pneumatically or capacitively coupled to the wafer, for sensing the distance d that each sensor 16 is from the wafer. Such distances d are converted into electrical signals that are sent through control loop 18 to a driver unit 20 that controls the vertical movement of rods 22, each rod being associated with its respective sensor 16. The rods 22 are kept properly spaced from each other by guide 24. Vertical movement of rods 22 in response to sensor signals, apply distorting forces to the silicon through the foil 10 an...