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Browse Prior Art Database

Read Only Store Patch

IP.com Disclosure Number: IPCOM000081279D
Original Publication Date: 1974-May-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 28K

Publishing Venue

IBM

Related People

Correy, RM: AUTHOR

Abstract

When digital computers employ read-only store (ROS) as a control or instruction memory, changes in the program or error conditions in the ROS require circuit changes. To avoid ROS circuit changes, so-called ROS patches have been employed. A particularly advantageous-ROS patch is described.

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Read Only Store Patch

When digital computers employ read-only store (ROS) as a control or instruction memory, changes in the program or error conditions in the ROS require circuit changes. To avoid ROS circuit changes, so-called ROS patches have been employed. A particularly advantageous-ROS patch is described.

The control memory of the processor employing the described technique has both ROS control memory and random-access memory, which is a writable store such as core storage or a semiconductive store. Both memories have good communication with processing circuits which include an arithmetic logic unit (ALU). As is common in digital computers, a start-up routine is established in ROS. This start-up routine may include initializing diagnostics, plus loading certain control constants and other instructions into random-access memory, as from a 23FD flexible disk file.

To employ the described technique, the initializing routine loads a pointer field and a patch field into random-access memory. The pointer field has one entry register for each of the test instructions T(O)-T(i). The test instructions are conditional branch instructions, which fetch the corresponding pointer register contents and test for its numerical value. If the test is 0, the program proceeds within ROS. If the test is nonzero, the program will branch away from ROS to the instructions lodged in the patch field, as pointed to by the numerical contents of the pointer entry. For example, if there is an error condition in ROS intermediate to the ROS registers containing T(1) and T(2) test instructions, then T(1) will have a pointer field which is nonzero. T(1) branches the program to the patch field via the pointer entry, with the patch instr...