Browse Prior Art Database

Sequence Verification

IP.com Disclosure Number: IPCOM000081280D
Original Publication Date: 1974-May-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Vermeulen, JC: AUTHOR

Abstract

In many control applications, sequences of operation represented by binary indicating status signals are predictable. Thus, verification that the control is operating properly can be achieved by verifying the predicted sequence. In accordance with the described apparatus and techniques, if a nonpredicted change occurs, an error is logged for indicating possible malfunctions in the control system, such as defective sensing apparatus. Temporary erroneous data can be skipped over without a need to repair or maintain the machine. Hence, if a nonpredicted change occurs immediately followed by a predicted change, the error is logged for future maintenance and the nonpredicted change is ignored to enable the machine to operate.

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Sequence Verification

In many control applications, sequences of operation represented by binary indicating status signals are predictable. Thus, verification that the control is operating properly can be achieved by verifying the predicted sequence. In accordance with the described apparatus and techniques, if a nonpredicted change occurs, an error is logged for indicating possible malfunctions in the control system, such as defective sensing apparatus. Temporary erroneous data can be skipped over without a need to repair or maintain the machine. Hence, if a nonpredicted change occurs immediately followed by a predicted change, the error is logged for future maintenance and the nonpredicted change is ignored to enable the machine to operate.

By way of example, a three-digit control sequence is checked in the above- described manner. The sequence has five control states respectively represented by the binary digits 100, 000, 010, 011, and 001. The sequence can be performed in either direction from end-to-end. In this sequence, it is predictable which bit is expected to change. Each predicted bit change is stored in a coded format; then, after the next change has occurred, the two changes are compared. In this manner, illegal changes from 000 to 001, for example, are detected; but also the changes in direction as by 000 to 010 to 000 are detected.

For hardware minimization, program table logic arrays (PLA) are utilized. These include search and read arrays constru...