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Precision Analog Current Switching Technique

IP.com Disclosure Number: IPCOM000081288D
Original Publication Date: 1974-May-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Related People

Schulz, RA: AUTHOR

Abstract

A compensating diode and switching diode(s) with matched characteristics improve accuracy of a digital-to-analog converter (DAC).

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Precision Analog Current Switching Technique

A compensating diode and switching diode(s) with matched characteristics improve accuracy of a digital-to-analog converter (DAC).

In a four-bit converter DAC (Fig. 1), reference voltage Eref is applied to operational amplifier A1 having matched input and feedback resistors R1. The output of A1 is -Eref-VD5, where VD5 is the voltage drop of compensating (reference) diode D5 in A1's feedback path. With all driver circuits (DR) cut off, currents set up in switching diodes D1-D4 are determined by (a) the voltage at summing junction 1 of operational amplifier A2, which is zero for an ideal amplifier, (b) value of the binary weighted resistors R, 2R, 4R, 8R, (c) difference in diode drop, i.e., V1, V2, etc. in the particular path and D5, and which for matched devices approaches zero, and (d) Eref and accuracy of A1 and resistors R1.

Under ideal conditions, the currents through D1, D2, D3, and D4 are Eref/d, Eref/2R, Eref/4R, and Eref/8R, respectively. Digital-to-analog conversions are effected by switching these precision weighted currents by cutting off D1-D4 with the DRs, or cutting off the ORs and letting the precision current flow into summing junction 1.

The diode voltage drops of D1 to D4 are matched to D5 by fabricating all diodes D1-D5 on a single monolithic integrated circuit chip 2, and insuring equal current density in D1-D5 by using parallel identical diodes. For the four-bit example, diode D4 is fabricated as a single diode; D3 as two diodes in parallel; D2 as four diodes in parallel; and D1 and D5 are each eight diodes in parallel. The current passing through each individual diode is thus EA/8R, where R1 = R. The summation of the binary-weighted currents at summing junction 1, is converted to an output voltage eout via A2 and feedback resistor Rf.

The schematic of the driver DR circuit is shown in Fig. 1. The circuit is TTL/DTL compatible and is capable of either cutting off the diode in the precision current leg (diodes D1-D4) or else being cut off, so that it does not contribute significant leakage current. When the input is down (near ground), the current path through DA, DB, and RB causes the base of 01 to be in the neighborhood of two diode drops below ground. The emitter of Q1 is tied to the precision current diode (D1 for example) which is clamped (by D1) to one diode drop below ground. Thus, the emitter of Q1 is slightly back biased and Q1 is cut off. Under these conditions, the precision current flows through its diode (D1) and into the A2 summing junction. The other state is achieved when the DR circuit input is up (>2.4 volts).

This causes the base of Q1 to go above ground, until it is clamped by forward biasing the base-collector of Q1. Under these conditions, Q1 is saturated and its emitter will sit at -VCE(SAT) (the saturation voltage) which is typically 100 mV below ground. This voltage is small enough that the precision current diode (D1 for instance) cannot condu...