Browse Prior Art Database

Sequential Control System

IP.com Disclosure Number: IPCOM000081292D
Original Publication Date: 1974-May-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 32K

Publishing Venue

IBM

Related People

Baldwin, BE: AUTHOR [+2]

Abstract

In certain types of data processing systems, it is desirable to closely identify the exact current portion of a subcycle of an operating cycle, in the event of a malfunction. Prior known controls for such data processing systems utilize logical combinations of conditions precedent to determine whether or not a subsequent operating condition should be initiated. In the event of a malfunction, it is difficult to determine which of the signals on the various combinations was at fault, depending upon the number of logical inputs to the control system.

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Sequential Control System

In certain types of data processing systems, it is desirable to closely identify the exact current portion of a subcycle of an operating cycle, in the event of a malfunction. Prior known controls for such data processing systems utilize logical combinations of conditions precedent to determine whether or not a subsequent operating condition should be initiated. In the event of a malfunction, it is difficult to determine which of the signals on the various combinations was at fault, depending upon the number of logical inputs to the control system.

To obviate such difficulties, the sequential control system illustrated requires that predetermined conditions be met for each stage of a multistage operating cycle, before the control situation is effective for the next stage of the cycle. As shown, a bistable device, such as a conventional trigger, is provided for each stage of operation, here illustrated as a plurality of triggers T1, T2, T3 and T4. Each of these triggers is of conventional form, having a set and reset input, and having outputs which are on or off depending upon whether or not the trigger has been set or reset. The outputs are designated for the on state of the trigger as A, B and C, and for the off or reset state of the triggers as NA, NB and NC. Thus, if trigger T1 has been set on, an output will be present at A, but no output will be present at NA. Conversely, with the trigger T1 in its reset state, an output will be present at NA, but no output will be present at A.

All of the triggers are provided with a common reset signal provided by a terminal R. When this signal is supplied, all triggers will be returned to their reset condition. The input to the set side of each of the triggers is the output of an AND circuit, designated by reference characters 3, 5, 7 and 9. A common input to each of these AND circuits is a timing pulse, supplied as one input to the AND circuits from a terminal TP. The timing pulse constitutes the principal synchronizing signal for the entire system, which is governed by this control sequencing arrangement.

Considering now AND circuit 3 which provides the set input to trigger T1, the other input to this AND circuit is a signal supplied from a terminal C1, this signal being present when conditions are such that the stage A of the operating cycle should be initiated. It will be apparent that with the signal present on line C1, when the synchronizing signal is presented at terminal TP, an output from AND circuit 3 will set trigger T1 to its on condition, at which time a signal will be present on line A and the signal on line NA will be removed. This combination of signals, with or without...