Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Hybrid Microprocessor

IP.com Disclosure Number: IPCOM000081305D
Original Publication Date: 1974-May-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 4 page(s) / 77K

Publishing Venue

IBM

Related People

Boehm, RF: AUTHOR [+5]

Abstract

Plural Programmed Logic Arrays (PLA) 10-13 are each connected through input bus 14 and output bus 15 to output register 16 and input register 17, respectively, of microprocessor 18. Each PLA is programmed to perform a function, similar to a large number of sequential steps of a microprogram, on command from microprocessor 18. Each PLA in effect is a subroutine in hardware form or a hardware macro. A suitable PLA would take the form of a Read-Only Storage (ROS) device, with fixed personality, or could be an electrically alterable ROS.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 59% of the total text.

Page 1 of 4

Hybrid Microprocessor

Plural Programmed Logic Arrays (PLA) 10-13 are each connected through input bus 14 and output bus 15 to output register 16 and input register 17, respectively, of microprocessor 18. Each PLA is programmed to perform a function, similar to a large number of sequential steps of a microprogram, on command from microprocessor 18. Each PLA in effect is a subroutine in hardware form or a hardware macro. A suitable PLA would take the form of a Read-Only Storage (ROS) device, with fixed personality, or could be an electrically alterable ROS.

For example, the PLA #1 is logically structured as an associative array to have a personality for performing an M out of N function, which requires the determination of the number of active bits in a register consisting of, for example, 8 or more bits. A usual microprogram would test each bit sequentially, in order to count the number of active bits. In the case of an 8-bit number, the number of cycles can be 40, if a microprogramming sequence is used. For PLA #1 in the form of an associative array, the PLA responds to all the information on bus 14 when presented simultaneously.

The structure and function of an M out N counter for PLA #1 is illustrated as follows. Consider an M of N counter where N = 4 bits (A, B, C, D). In the 16 possible combinations of 4 bits the terms for M from 0 to 4 are listed below: Binary Value

M of M Product Terms (Output) 0 000 A B C D 1 001 A B C D + A B C D + A B C D + A B C D 2 010 A B C D + A B C D + A B C D + A B C D + A B C D + A B C D 3 011 A B C D + A B C D + A B C D + A B C D 4 100 A B C D.

In a PLA the Search Array ('AND' array) is personalized to find the product terms. The Search Array feeds another array which provides the OR function to generate the Sum of Products shown above. The resultant Sums of Products can drive the prop...