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AC Pulse and Chip Delay Predictor

IP.com Disclosure Number: IPCOM000081319D
Original Publication Date: 1974-May-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 4 page(s) / 37K

Publishing Venue

IBM

Related People

Chao, CC: AUTHOR [+2]

Abstract

A system is described that performs two functions in support of AC testing of large-scale integrated (LSI) logic chips. For each chip I/O where an AC pulse train is to be applied, the minimum pulse width and period are predicted. Also, the response time for any chip output to change state as a result of the input stimulus is predicted.

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AC Pulse and Chip Delay Predictor

A system is described that performs two functions in support of AC testing of large-scale integrated (LSI) logic chips. For each chip I/O where an AC pulse train is to be applied, the minimum pulse width and period are predicted. Also, the response time for any chip output to change state as a result of the input stimulus is predicted.

The system requires as input, a digitized description of the logic contained on the chip to be tested and a set of AC test patterns. Each pattern should consist of input stimuli (single pulse or pulse train) and DC bias conditions on the remaining input pins that are not pulsed.

All predictions are in terms of time units. Each time unit equals a unit logic block delay. A unit block delay may be defined as an approximate logic circuit block's propagation delay, say, 1 nanosecond. All logic circuits on a chip are assumed to have the same unit delay.

Initially, the input pulse in each AC test pattern is transformed, by superposition, into three equivalent DC logic patterns. A positive pulse P, becomes logic 0-logic 1-logic 0. A negative pulse N, logic 1-logic 0-logic 1. The DC biases in terms of logic 0 and 1's at all other inputs remain unchanged. The transformed test patterns are applied to the simulation program. The pulsed input is supplied with each of the 3 equivalent DC patterns in succession under controlled duration. The corresponding expected pulsed output responses are automatically produced.

The simulator processes one test pattern at a time. Each time unit allows each logic circuit block to propagate a signal from its input to its output(s). An input signal will eventually propagate to the chip outputs after a certain number of time units. By monitoring the output responses as well as the input stimuli, the input pulse width and period, as well as path delays, may be determined.

The system operates at three steps for each given AC test pattern. Each step corresponds to the time that one of the pulse transformed 3 equivalent DC levels is applied at the simulator. For example, if the test pattern specified a positive pulse P at an input pin, the pulse would be decomposed into 3 DC levels; logic 0 (hereafter to be called Step 1 level), then logic 1 (Step 2 level), and finally, logic 0 (Step 3 level).

Details of how to obtain pulse width, period and turn-on, turn-off delays are briefly described in the 3 steps as follows: STEP 1 1.1 All internal logic circuit block inputs and outputs in

simulator are set to unknown (X).

1.2 Unit time counter is set to zero.

1.3 Apply test patter at inputs of simulated chip. A Step

1 level is applied at the pulsed input.

1.4 Proceed with simulation at unit time intervals while

counting unit times. At the end of each unit time, each

output is monitored.

1

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1.5 As soon as an output changes state, the corresponding

total number of time units is recorded for that output.

Since a unit time equals one logic circuit block

(...