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Complementary Transistor Switch Memory Cell

IP.com Disclosure Number: IPCOM000081321D
Original Publication Date: 1974-May-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Dorler, JA: AUTHOR [+3]

Abstract

The complementary transistor switch (CTS) memory cell, Fig. 1, circumvents the inherent restrictions of high-power requirements. This cell allows higher bit density with reliable cell stability, and high-speed operation simultaneous with low-power requirements.

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Complementary Transistor Switch Memory Cell

The complementary transistor switch (CTS) memory cell, Fig. 1, circumvents the inherent restrictions of high-power requirements. This cell allows higher bit density with reliable cell stability, and high-speed operation simultaneous with low-power requirements.

Replacing the resistive load cell by a CTS cell, results in a compact design essentially limited only by photolithographic constraints. Since the levels within the cell are established only by junction voltages, rather than linear IR drops, the cell can be made to operate at low-current levels. The-use of a Schottky diode for "on-off" level definition has the further benefit of preventing saturation.

This circuit using a PNP driving the base of an NPN, results in minimal frequency requirements for the PNP, and encourages the use of a lateral PNP/vertical NPN as an integrated device.

In typical cell operation, the conducting side A defines the "0" or low potential, and also establishes the internal bias such that the opposite side B is held off and defines the "1", or high potential.

To change state, the off side of the cell is caused to conduct by the application of an appropriate signal applied to its write input line. In Fig. 2, a current signal is employed. In Fig. 3, a voltage signal is employed. In both Figs. 2 and 3, reading is accomplished by differentially sensing the respective Schottky diodes.

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