Browse Prior Art Database

Sliding Index Coding

IP.com Disclosure Number: IPCOM000081326D
Original Publication Date: 1974-May-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 57K

Publishing Venue

IBM

Related People

Latestere, G: AUTHOR

Abstract

This sliding index coding technique permits transmission of low-speed asynchronous data at a higher bit rate through coding of the data value, as well as coding of the instants of transition in the data values. The coding of transition times with respect to a higher speed clock permits the handling of input data which is subject to asymmetrical distortion, together with discrepancies that may exist between the input data rate and the internal clock of the transmitter.

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Sliding Index Coding

This sliding index coding technique permits transmission of low-speed asynchronous data at a higher bit rate through coding of the data value, as well as coding of the instants of transition in the data values. The coding of transition times with respect to a higher speed clock permits the handling of input data which is subject to asymmetrical distortion, together with discrepancies that may exist between the input data rate and the internal clock of the transmitter.

The principle of the sliding index coding will be described in an example where the average data rate is 1200 data elements per second, the transmission speed on the line being 4800 bits per second.

As shown in Fig. 1, each 1/4800 sec time interval of the clock (ref. line 1A) is divided into four 1/19200 sec subintervals, respectively, coded 0 0 ; 0 1 ; 1 0 ; 1 1. After each transition in the stream of the original data elements (ref. line 1b), the following bit sequence is found, at the 4800 bps rate: Bit 1 = data value.

Bit 2 and bit 3 = the 2-bit coding of the 1/19200 sec subinterval in which transition occurred.

Bit 4 = the new data value if a new transition occurred in the last 1/4800 sec time interval (in this case, it is in fact the

first bit of the following sequence).

Bit 4 = the bit 1 repeated if no transition occurred.

Bit 4 is repeated at each successive bit time, as long as no further transition occurs.

Due to small discrepancies between the input data rate and the actual 1/1200 sec time interval of the average data clocks, the resulting bit sequences (or bit words) can be 3, 4 or 5-bits long.

Fig. 1 shows the three cases in 1A, 1B, 1C, in 2A, 2B, 2C, and in 3A, 3B, 3C, respectively.

For the first case, the input data (value 1) transition (line 1B) occurs in subinterval 1 0 (see line 1A) and the transition for the next data (value 0) occurs in subinterval 1 1 ; this results in the 4-bit sequence: 1 1 0 1 (see line 1C) on the high-speed line. As shown in the figure, the transition to the value 1 results in bit 1 of the sequence being of value 1. The code corresponding to the subinterval where transition occurs results in bits 2 and 3 being of respective values 1 and 0, and due to the fact that no transition occurred before the next bit time results in bit 4 being the repetition of bit 1 (dashed arrow); the following bits 0 1 1 are the first three bits of the sequence for the following data element.

For the second case, the data transition (value 1) occurs in sub-interval 0 0 (see lines 2B, 2A) and the transition for the next data (value 0) occurs in subinterval 1 1 ; this results in the 3-bit sequence 1 0 0 (see line 2C). The following bit 0 is the first bit of the next sequence corresponding to the next data.

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For the third case, the input data transition occurs in subinterval 1 1 (see lines 3B, 3A), the transition for the next data occurs in sub-interval 0 0. This results in the 5-bit sequence 1 1 1 1 1. The first three...