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Multiplex Digital Filtering Technique

IP.com Disclosure Number: IPCOM000081327D
Original Publication Date: 1974-May-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Thirion, P: AUTHOR

Abstract

Described is a technique for multiplexing digital filtering operations in cases when the input signal to be filtered is sampled with a sampling period shorter than the digital filter elementary delay.

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Multiplex Digital Filtering Technique

Described is a technique for multiplexing digital filtering operations in cases when the input signal to be filtered is sampled with a sampling period shorter than the digital filter elementary delay.

In the field of data transmission channel equalization, in particular, it is sometimes desirable to submit a data signal to two filtering operations in parallel. For many reasons, the input signal to be filtered is generally sampled at a rate higher than the reciprocal of the elementary delay of the digital filter delay line.

The proposed technique permits advantage to be taken of the full computing power of present multiplex digital filter structures. It will be described on a typical example of implementation.

Let it be assumed that an input signal x(t) is to be submitted to two filtering operations in parallel. Signal x(t) is sampled at a sampling rate of 14.4 kHz and the filters are twelve coefficient transversal digital filters, with an elementary delay T = 1/2400 second. Moreover, the sampling frequency at the output of both filters is chosen equal to the input sampling rate (14.4 kHz). Coefficients of the first filter will be referred to as c(i) and coefficients of the second one as d(i).

Such coefficients, under the forrm of binary words, are serially circulated at a shift rate of 115.2 kHz through the filter delay line 1 and looped back to the input of it through one-word delay element 2, six-word delay section 3, summing device 4 and one-word delay element 5, as shown on the drawing. Summing device 4 is intended to permit modification of the coefficients according to increments received on its second input. Delay line 1 is comprised of two eight- word delay sections, and is provided with three taps T(1), T(2), T(3) which supply inputs X(1), X(2), X(3) to arit...