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High Speed Four Bit Adder

IP.com Disclosure Number: IPCOM000081330D
Original Publication Date: 1974-May-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Beraud, JP: AUTHOR

Abstract

A high-speed field-effect transistor (FET) binary adder is described, which uses only AND, Inverters, NOR and AOI (AND OR Invert) circuits.

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High Speed Four Bit Adder

A high-speed field-effect transistor (FET) binary adder is described, which uses only AND, Inverters, NOR and AOI (AND OR Invert) circuits.

The problem of minimizing the operating time delay of an adder, and particularly the time delay due to carry processing, is solved by combining different types of full adders in the same adder.

An example is described for adding two four-bit words, while taking into account a previous carry bit Cy(o).

As shown on the figure, while a first type of full adder is used for stages 2 and 3, a second type is used for stages 1 and 4. Both types may be implemented by using only NAND, NOR, Invert and AOI circuits, as mentioned above. The first type provides an inverted carry output, e.g., for instance the carry output of stage 2 is:

(Image Omitted)

In view of the above, the arrangement described may be understood. The first stage is fed with the bits A(1), B(1) of the two words to be added, and with the previous carry, if any, and provides a sum bit Epsilon and a carry bit Cy(1). The second stage fed with A(2), B(2) and Cy(1) provides a sum bit epsilon(2) and an inverted carry bit Cy(2). At the input of stage 3, two inverters are used to invert bits A(3) and B(3) and provide A(3), B(3), which added to Cy(2) on a so- called first type full adder provides by Cy(3) and Epsilon(3). A third inverter I is used to provide the true value of bit Epsilon(3). The fourth stage, fed with Cy(3), A(4) and B(4) provides bit E...