Browse Prior Art Database

Sense System

IP.com Disclosure Number: IPCOM000081337D
Original Publication Date: 1974-May-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Gschwendtner, J: AUTHOR [+3]

Abstract

Fig. 1 shows a conventional sense latch in complementary metal-oxide semiconductor (CMOS) technology, as it is provided for each column of integrated, mostly identical memory cells between bit lines B0 and B1.

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Sense System

Fig. 1 shows a conventional sense latch in complementary metal-oxide semiconductor (CMOS) technology, as it is provided for each column of integrated, mostly identical memory cells between bit lines B0 and B1.

The disadvantages of such a pulsed sense system are:
a) A set pulse is required which has to be generated either on the

chip proper or which has to be supplied from the outside. The

pulse skew leads to an increase in the-access time.
b) The voltage differential between the two bit lines develops

only slowly, since they are loaded by the latch node

diffusions at nodes A' and B'. And,
c) The input and output of the latch are identical.

Fig. 2 shows a new sense system in CMOS technology which requires no set pulse. The circuit consists of the actual latch with transistors, N5, N6, P1, P2, plus a new write/isolation stage with transistors P8, P4 and P7, P3, respectively. The transistor designations N or P denote whether the respective field-effect transistor (FET) is an N or a P channel device. By suitably biasing bit lines B0, B1, preferably to VH-VT, all transistors become nonconductive. The bias is chosen so low that a low-voltage differential between the bit lines, which is caused by memory cell selection, sets the latch of the sense system.

For setting on N5, P4 must have a low resistivity so as to overcome the low resistance of transistor N6 in the on state. A low-resistivity transistor P4 subjects bit line B1 to a high capacity, thus produci...