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Browse Prior Art Database

Content Addressable Storage Cell

IP.com Disclosure Number: IPCOM000081340D
Original Publication Date: 1974-May-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Berger, HH: AUTHOR [+4]

Abstract

Fig. 1 shows a bipolar flip-flop storage cell which in contrast to a conventional read/write storage cell, permits associative operation without requiring additional components or lines.

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Content Addressable Storage Cell

Fig. 1 shows a bipolar flip-flop storage cell which in contrast to a conventional read/write storage cell, permits associative operation without requiring additional components or lines.

In the standby state diodes D] and D2 are so biased that there is no diode current flow. Of the applied cell current Io, the alpha PNP. Io part flows into the X-line, so that the voltage drop VX on resistor RX corresponds to the following equation VX = RX . alpha PNP . Io . nx. where nx denotes the number of cells on the X-line. To reduce power dissipation to a minimum, a very low-cell current Io can be used.

As the cell information is read, a negative voltage pulse is applied to the X- line and a positive pulse to the Y-line. This leads to the two bit line resistors R2 and R1 being connected parallel to the load elements of the storage cell via decoupling diodes D2 and D1, respectively. Ohmic resistors R1, R2 can be replaced by other load elements, such as PNP transistors. The voltage difference between cell nodes C1 and C2 is transferred to bit lines B0 and B1 via diodes D2, D1. By a sense amplifier, not shown, whose inputs are connected to bit lines B0, B1, the state of the storage cell can be determined very rapidly.

During writing, the same pulses are applied to the X- and Y-lines as during reading. However, deviating from the read operation, a negative pulse is applied to bit line B0 when a "1" is written (T1 ON), so that an additional current enters the cell only via diode D1 but not via diode D2. The current through D1 flows into the base of T1, causing the latter to be set ON. In comparison with cell current Io, this additional current ID1 must be chosen high (ID1 > beta NPN Io/2) to ensure that transistor T2 is set OFF.

During searching, an incomplete write operation is carried out. In a 1 search, the potential of bit line B1 is increased by about 300 mV - 500 mV (diode threshold voltage) over the X-line. If a 1 has been stored (T1 ON), then no additional current flows into the cell via D1. Analogously, in a "0" search the bit line potential of B0 is increased. In this case where a 1 is stored (T1 ON), an additional current flows into the collector of T1. This additional current causes an increase in the voltage drop across RX, which serves to indicate that a mismatch exists....