Browse Prior Art Database

Priority Controlled Mutual Exclusion Through a Single Wire Bus

IP.com Disclosure Number: IPCOM000081341D
Original Publication Date: 1974-May-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Fleck, M: AUTHOR [+2]

Abstract

Processors contending for the use of a serially reusable resource (SRR) must dispose of a means, which guarantees mutually exclusive granting of the SRR for any order in which requests are raised. If the contending processors are not subject to a common synchronization discipline, no assumptions can be made on the relative timing of request raising.

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Priority Controlled Mutual Exclusion Through a Single Wire Bus

Processors contending for the use of a serially reusable resource (SRR) must dispose of a means, which guarantees mutually exclusive granting of the SRR for any order in which requests are raised. If the contending processors are not subject to a common synchronization discipline, no assumptions can be made on the relative timing of request raising.

The proposed hardware achieves mutually exclusive use of an SRR in all conceivable systems and situations, by means of the absolute minimum of dedicated nonprivate hardware: a common bus consisting of a single wire (plus ground) only. This bus may connect to an arbitrary number of "interaction controllers" which, in turn, connect one-by-one to each of the processors. The SRR is granted to that processor which raises a request with highest priority.

The circuits of an interaction controller are initialized by switching the "raise/cancel in" line from the ON to the OFF position.

This resets monostable flip-flop 3 and flip-flops 7 and 8, because the output of OR gate 5 is switched from OFF to ON. AND gate 9 is OFF, AND gate 10 is ON. Since generators (GEN) are defined to put out a defined DC voltage only if the input is ON, generators 12 and 13 do not generate a defined voltage but generator 14 generates voltage zero. "Grant out" is switched OFF.

When switching the raise/cancel in line from the ON to the OFF position, the output of AND gate 2 is either switched from ON to OFF or it remains OFF. Because only a switching from OFF to ON may set monostable flip-flop 3 and flip-flop 7, no setting of flip-flops 3 and...