Browse Prior Art Database

Time of Day Clock Synchronization Among Multiple Processing Units

IP.com Disclosure Number: IPCOM000081363D
Original Publication Date: 1974-May-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 79K

Publishing Venue

IBM

Related People

Smith, RM: AUTHOR

Abstract

This is a circuit and method for synchronizing and checking a plurality of time-of-day (TOD) clocks in a multiprocessing system. Hardware synchronizes the low-order part of the TOD clocks and a method synchronizes the high-order part in the same clocks, by using carry pulses derived from an intermediate bit position in each TOD clock. The carry pulses from all TOD clocks are combined in an OR circuit with each clock, to provide common carry pulses for synchronizing each TOD clock in the system.

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Time of Day Clock Synchronization Among Multiple Processing Units

This is a circuit and method for synchronizing and checking a plurality of time-of-day (TOD) clocks in a multiprocessing system. Hardware synchronizes the low-order part of the TOD clocks and a method synchronizes the high-order part in the same clocks, by using carry pulses derived from an intermediate bit position in each TOD clock. The carry pulses from all TOD clocks are combined in an OR circuit with each clock, to provide common carry pulses for synchronizing each TOD clock in the system.

The shown TOD circuit for CPU C is identical to those for CPU's A through N in the multiprocessing system. TOD clock 10 comprises 52 binary connected flip-flop circuits, 0 through 51. A crystal oscillator and pulse former 15, common to all clocks in the system, drives the lowest order position 51 of clock 10 at a one megahertz rate. At this rate, a carry pulse occurs out of bit position 32 into position 31 approximately once a second. Pulses from position 32 in each clock 10 in each CPU are connected through a pulse former 11 to a carry pulse line 12. Former 11 generates a pulse having about a one microsecond duration upon the rise of the carry voltage from position 32.

Inputs to an OR circuit 16 and an AND circuit 17 are connected to line 12 in CPU C, and to the carry pulse lines from all other CPU's A through N in the system. Common carry pulses are provided on output line 18 from OR 16 to AND circuits 26 and 41. The common carry pulses are used for two purposes:
(1) to put any stopped clock into synchronism with any other operational clock being used as a standard, and (2) to continuously check to determine if the TOD clocks are in synchronization.

For checking, the common carry pulses are time compared in a synchronization check circuit comprising OR 17, AND's 17, 26 and 27, inverter 28, delay 32 and trigger 29. Outputs of AND's 26 and 27 control the set (S) and reset (R) inputs of trigger 29, which provides a TOD clock synch-check signal, indicating that the TOD clocks are not in synchronism, on its true (t) output line
31.

Coincidence among the carry pulses in AND 17, provides an output signal which enables AND 27 to reset trigger 29. The output of AND 17 is inverted by circuit 28, thus blocking the output of AND 26. AND 26 also receives the common carry pulses from OR 18, and delayed pulses from oscillator 15. An output is provided by inverter 28 to enable AND 26 if coincidence is lacking among the inputs to AND 17, due to lack of synchronism in one or more of the inputs provided to it from any of the clocks in the system. When clock 10 is out of synchronism, triggers 29 in all CPU's signal an interrupt condition, which alerts the program that synchronization action is required, thus initi...