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Latching Logic Circuit Without Standby Power Dissipation

IP.com Disclosure Number: IPCOM000081383D
Original Publication Date: 1974-May-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Jutzi, WW: AUTHOR

Abstract

An OR logic gate is proposed which latches when set for later transfer of the logic results, and which does not consume power except in its dynamic state. The gate consists of a superconducting loop connected to a word pulse source. In one of the two branches of the loop a plurality of Josephson junctions can be arranged, which are controllable by control lines carrying input variables.

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Latching Logic Circuit Without Standby Power Dissipation

An OR logic gate is proposed which latches when set for later transfer of the logic results, and which does not consume power except in its dynamic state. The gate consists of a superconducting loop connected to a word pulse source. In one of the two branches of the loop a plurality of Josephson junctions can be arranged, which are controllable by control lines carrying input variables.

When the word pulse is applied simultaneously with one or more of the input variables, current flow occurs only in the branch having no Josephson junctions. Upon removal of the word current and input variable, a circulating current is trapped within the loop (latching). The circulating current is used as the control current for a sense junction, which has to be supplied with a sense current for transfer of the logic result.

A reset junction of a size larger than the input junctions is provided for cancelling the loop current. The reset junction is to be in the loop branch without input junctions, if the word current is replaced by a constant-bias current.

The NOR function of the gate can be changed to an OR function by replacing the unsymmetrical sense gate characteristic by a symmetrical one, i.e., by replacing the inline gate by a crossline gate.

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