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Clocked Power Supply for Josephson Tunneling Circuits by Capacitive Coupling

IP.com Disclosure Number: IPCOM000081401D
Original Publication Date: 1974-May-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Anacker, W: AUTHOR

Abstract

Josephson tunneling logic circuits are connected to power supply lines via capacitors, as shown in Fig. 1. A pulse voltage source, Vin, is coupled to a plurality of Josephson devices G1-Gn via capacitors C1-Cn and optional current limiting devices J1, Jn. Each of the Josephson devices G1-Gn has control lines L1-Ln, respectively, associated therewith and each Josephson device is terminated by resistors R1-Rn, respectively.

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Clocked Power Supply for Josephson Tunneling Circuits by Capacitive Coupling

Josephson tunneling logic circuits are connected to power supply lines via capacitors, as shown in Fig. 1. A pulse voltage source, Vin, is coupled to a plurality of Josephson devices G1-Gn via capacitors C1-Cn and optional current limiting devices J1, Jn. Each of the Josephson devices G1-Gn has control lines L1-Ln, respectively, associated therewith and each Josephson device is terminated by resistors R1-Rn, respectively.

In operation, a voltage pulse from Vin is applied ior the activation of all circuits connected to power supply line 1. The applied voltage pulse (Fig. 2) is characterized by an amplitude Vm; its ramp-like leading edge by a rise time tR; its top width by tt and its fall time by tf. The rise time tR is chosen to be equal to the logic cycle time of the network under consideration. Then the amplitude Vm is determined according to: Igate = C Vm Over tT. which implies that a constant- gate current, Igate, flows through all gates during the rise time of the applied voltage pulse. During tt, no current flows through gates G1 - Gn and, hence, tt can be chosen long enough to assure that switched gates return to the zero voltage state (without causing punch-through). The time, tf is chosen such that the gate current in the opposite direction does not switch any gate out of the zero voltage state.

Fig. 2 indicates the voltage, V, the current, I, and the electric charge, Q, waveforms obtained when a gate does not switch and when a gate switches. Thus, waveforms Vin,I1, Vc...