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Error Detection and Correction Apparatus

IP.com Disclosure Number: IPCOM000081418D
Original Publication Date: 1974-Jun-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Thompson, GH: AUTHOR

Abstract

In a magnetic tape storage apparatus, data signals stored laterally with respect to the length of the tape contain error detection and correction residues. The data is arranged in blocks of data registers 0-B, for example. Depending on the mode of reading the data in the various data registers, error conditions occurring in such data registers can exceed the error correction capability of the stored residues. Accordingly, for example, the signals stored in data register #6 may not be recoverable. By adding an error checking and correction (ECC) data register at one end of the block of registers and identifying the data register in error, the data signals can be successfully reconstructed.

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Error Detection and Correction Apparatus

In a magnetic tape storage apparatus, data signals stored laterally with respect to the length of the tape contain error detection and correction residues. The data is arranged in blocks of data registers 0-B, for example. Depending on the mode of reading the data in the various data registers, error conditions occurring in such data registers can exceed the error correction capability of the stored residues. Accordingly, for example, the signals stored in data register #6 may not be recoverable. By adding an error checking and correction (ECC) data register at one end of the block of registers and identifying the data register in error, the data signals can be successfully reconstructed.

Data signals to be stored are initially buffered into a memory which is addressed through an address register, as sequenced by the control circuits. Additionally, the output of the memory is supplied through switch 10 to a data register for recording on the storage medium. Interleaved between data signal transmissions to the registers is an error correction accumulator cycle. A designated portion of the memory is reserved for the ECC residue to be recorded in the ECC data register.

After each data word has been supplied to the data register, switch 10 is actuated; and the memory accumulator area is accessed for supplying the residue to the ECC residue register. The outputs of the ECC residue in the data register are bit added or exclusive OR'd and then restored into the accumulator area. These two steps are repeated until all...