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Digital Controlled Phase Shifting

IP.com Disclosure Number: IPCOM000081419D
Original Publication Date: 1974-Jun-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

McDonald, EG: AUTHOR [+2]

Abstract

In magnetic recording systems, it is often desirable to phase shift certain signal transitions to compensate for perturbations in signals caused by recording channel characteristics. Such characteristics include the inductance of the record and reproduce heads. In some instances, depending on the data pattern, i.e., the wavelength characteristics of the signal being recorded, the transition can be advanced or retarded in phase. In a modified frequency-modulated encoded signal (MFM), the data pattern has limited wavelength variations. There is a tendency to close the longer wavelengths, i.e., make them shorter, and broaden the shorter wavelengths. Hence, in recording such a signal, the longer wavelengths should be made longer at the expense of the shorter wavelengths.

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Digital Controlled Phase Shifting

In magnetic recording systems, it is often desirable to phase shift certain signal transitions to compensate for perturbations in signals caused by recording channel characteristics.

Such characteristics include the inductance of the record and reproduce heads. In some instances, depending on the data pattern,
i.e., the wavelength characteristics of the signal being recorded, the transition can be advanced or retarded in phase. In a modified frequency-modulated encoded signal (MFM), the data pattern has limited wavelength variations. There is a tendency to close the longer wavelengths, i.e., make them shorter, and broaden the shorter wavelengths. Hence, in recording such a signal, the longer wavelengths should be made longer at the expense of the shorter wavelengths.

The illustrated digital phase shifter also may be used for information phase modulating, which provides for both advance and retard changes in the phase.

Typical input data patterns are shown, which result in certain data paths being selected in the data path logic from the first or input shift register. The output of the data path logic supplies signals to gates 1-9, in accordance with the equations set forth adjacent the input data patterns. The resultant compensation is also tabulated adjacent the AND gate enumeration. The AND gates 1-9 output to respective register positions of the second or output shift register. A common clock, not shown, times the shift regist...