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Insulated Gate FET Memory Chip Low Capacitance Bit Line Structure

IP.com Disclosure Number: IPCOM000081424D
Original Publication Date: 1974-Jun-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Garnache, RR: AUTHOR

Abstract

It is desirable in the utilization of field-effect transistor (FET) single-device memory cells having capacitor and field shield elements incorporated in the integrated circuit structure, to maintain low-capacitance bit-line properties without adding significant thermal cycles in the processing steps and compromising field shield effectiveness.

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Insulated Gate FET Memory Chip Low Capacitance Bit Line Structure

It is desirable in the utilization of field-effect transistor (FET) single-device memory cells having capacitor and field shield elements incorporated in the integrated circuit structure, to maintain low-capacitance bit-line properties without adding significant thermal cycles in the processing steps and compromising field shield effectiveness.

This result is accomplished by allowing or providing for a layer of intrinsic polycrystalline silicon over the bit line, and utilizing a doped polycrystalline layer as a field shield in other areas of the structure.

A suitable silicon substrate having appropriate diffused source and drain regions formed by drive-in, ion implantation and the like techniques, is provided with an insulating layer of silicon dioxide and/or nitride-oxide composite. Over this is superimposed a layer intrinsic polycrystalline silicon, followed by a layer of pyrolytic silicon dioxide. Then the diffused substrate area to be utilized as a bit line is masked and the upper oxide layer removed, allowing a layer of intrinsic polycrystalline and silicon dioxide to cover the bit line diffusion. The remaining intrinsic polycrystalline silicon is capable of being diffused or doped with the desired impurity.

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