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Low Capacitance Semiconductor Bit Line Profile

IP.com Disclosure Number: IPCOM000081425D
Original Publication Date: 1974-Jun-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Kruggel, RH: AUTHOR [+2]

Abstract

Where it is desirable to minimize or eliminate stray capacitance over bit line configurations in semiconductor single-device cell structures, having a polycrystalline silicon field shield incorporated therein, and the structure comprises diffused areas covered by a insulating layer of silicon dioxide and silicon nitride and having a polycrystalline silicon layer thereon, the following process steps accomplishes the low-capacitance condition: a) Deposit silicon nitride, about 200 angstroms, on the polycrystalline silicon layer; b) Selectively etch nitride away from the areas where low capacitance is desired, e.g., bit lines, to expose underlaying polycrystalline silicon and c) Thermally oxidize polycrystalline silicon to the underlaying nitride-oxide insulating composite layer.

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Low Capacitance Semiconductor Bit Line Profile

Where it is desirable to minimize or eliminate stray capacitance over bit line configurations in semiconductor single-device cell structures, having a polycrystalline silicon field shield incorporated therein, and the structure comprises diffused areas covered by a insulating layer of silicon dioxide and silicon nitride and having a polycrystalline silicon layer thereon, the following process steps accomplishes the low-capacitance condition:
a) Deposit silicon nitride, about 200 angstroms, on the

polycrystalline silicon layer;
b) Selectively etch nitride away from the areas where low

capacitance is desired, e.g., bit lines, to expose

underlaying polycrystalline silicon and
c) Thermally oxidize polycrystalline silicon to the underlaying

nitride-oxide insulating composite layer.

The above method forms a thick oxide over the bit line area.

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