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Variable Power Performance Circuit

IP.com Disclosure Number: IPCOM000081426D
Original Publication Date: 1974-Jun-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Gersbach, JE: AUTHOR

Abstract

Described is a technique for variation of a memory chip in which peripheral circuits are pulsed on by the coincidence of two logic signals, so that the delay through the powering circuits is included in the total delay of the chip.

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Variable Power Performance Circuit

Described is a technique for variation of a memory chip in which peripheral circuits are pulsed on by the coincidence of two logic signals, so that the delay through the powering circuits is included in the total delay of the chip.

By forcing the powering circuits of the array to be continuously energized, the delay is much less but the power is larger. The basic system shown uses inputs A and B to activate the power gate 10 and the current reference circuit 11 in the low power-performance mode. The logic circuit 12 so utilized provides an output 13 which is a function of the logic inputs C and D, which also may or may not include inputs A and B.

The power utilized by the circuit is the standby power required in the power gate circuit, plus the duty cycle of input signals A and B times the power in the current reference circuit 11 and logic circuit 12. If the power supply is not connected to the circuit as shown, the power gate and, therefore, the current reference circuit 11 and the logic circuit 12 is continuously powered-out. This continuous powering reduces the delay from the input to the output, to that of the delay of the logic circuit 12 only. In this continuous power mode, there is no reduction in power due to the duty cycle of inputs A and B.

In this way, an arrangement for variation of the power performance of a semiconductor circuit by forcing the circuits to be continuously energized has been described.

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