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Complementary Bipolar Device Structure

IP.com Disclosure Number: IPCOM000081427D
Original Publication Date: 1974-Jun-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Chang, JJ: AUTHOR [+2]

Abstract

A high-performance low-power logic circuit and memory cell can be constructed with complementary devices, in which both vertical PNP and NPN transistors are featured. The NPN transistor structure produced is identical to the standard buried subcollector structure, except that the P type isolation region surrounding the active device is composed of the P+, PNP subcollector region, the NPN base region, and the PNP emitter region on the lateral boundaries, and further is composed of a thin P layer, beneath the NPN subcollector, formed by ion implantation or a mixed source subcollector diffusion.

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Complementary Bipolar Device Structure

A high-performance low-power logic circuit and memory cell can be constructed with complementary devices, in which both vertical PNP and NPN transistors are featured. The NPN transistor structure produced is identical to the standard buried subcollector structure, except that the P type isolation region surrounding the active device is composed of the P+, PNP subcollector region, the NPN base region, and the PNP emitter region on the lateral boundaries, and further is composed of a thin P layer, beneath the NPN subcollector, formed by ion implantation or a mixed source subcollector diffusion.

The PNP transistor is isolated by the N epitaxial layer and the N-substrate. The P+ collector surrounds the epitaxial base region, isolating it from the N type epitaxial region and the N- substrate region. The same diffusion used to form the NPN emitter region forms the PNP base contact. A separate P+ diffusion is required to form the PNP emitter region. Thus vertical PNP transistors can be fabricated on the same chip with vertical PNP transistors, by using only five diffusion masks.

As shown in the drawing, a first mask is utilized to produce both the P type isolation layer 10 and the PNP subcollector region 11. A second mask is then utilized to produce the PNP transistor subcollector region 12 and the P+ isolations 13 on the NPN transistor. Following these diffusions, an N type epitaxial layer 14 is deposited in which both the PNP col...