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Dual True/Dot Complement Multiplexer

IP.com Disclosure Number: IPCOM000081438D
Original Publication Date: 1974-Jun-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 43K

Publishing Venue

IBM

Related People

Stoops, EH: AUTHOR

Abstract

This multiplexer allows a normally slower second bus to go faster than a normally fast first bus.

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Dual True/Dot Complement Multiplexer

This multiplexer allows a normally slower second bus to go faster than a normally fast first bus.

The Dual True/Dot Complement Multiplexer has two channels 10, 11. The four NANDs 1, 2, 3, 4 of channel 10 are dotted together to feed NOR W connected to bus 12. ANDs 5, 6, 7 and the DOT NORs S and T of channel 11 feed the dottable complement output/input bus 13. The true output bus 12 feeds receivers, not shown, of the associated computer. The complement bus 13 is connected to other dottable drivers, not shown, and receivers, not shown, within and/or perhaps outside the computer and is buffered from bus 12. Thus, the faster bus 12 does not drive all the capacitive loading associated with the larger and slower bus 13.

Control signals A, B and C are mutually exclusive and are also mutually exclusive from those signals which turn on other drivers that are dotted onto bus
13. If signal A is a 1, DATA 1 is fed via NAND gate 2 of channel 10 into NOR W and appears as data on bus 12. DATA 1 also feeds via AND gate 5 of channel 11 into NOR S and is dotted on the large bus 13 as a complement signal. Thus, there is true DATA 1 on the true output 12 and its complement on the dottable output 13. Since signal A is a 1, signal A B C is a 0 and thereby disables AND gate V which feeds NOR W. Thus, the slow dot bus 13 is disabled from feeding into NOR W. As a result, NOR W follows the faster input from the dotted NAND gates 1-4 instead of the slower input from the dot bus 13.

To feed either DATA 2 or DATA 3 through the multiplexer, the corresponding control signal B or C, respectively, must be UP, i.e., a 1. The operation in this case is similar to that described for DATA 1 and control signal A.

The multiplexer is self-disabling with signals A, B, and C all DOWN or 0's, the signal A B C thus being a 1. This inhibits the three data inputs, DATA 1, DATA 2, or DATA 3 through the multiplexer.

More particularly, with an UP level in signal A B C, the dotted output of NAND gates 2-4 are forced to DOWN levels by the DOWN level of NAND gate 1. With the upper input of NOR W conditioned by this DOWN level, the output of gate W follows its other input and hence, the data from AND gate V which is concurrently being enabled by the UP level of signal A B C. Gate V in turn follows its other input, which is connected to b...