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Extending Utility of Data Flow Working Registers

IP.com Disclosure Number: IPCOM000081439D
Original Publication Date: 1974-Jun-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Patzer, WJ: AUTHOR

Abstract

To extend the utility of data flow working registers, a small local store contains the actual operands while time sharing a limited number of hardware working registers in the data flow.

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Extending Utility of Data Flow Working Registers

To extend the utility of data flow working registers, a small local store contains the actual operands while time sharing a limited number of hardware working registers in the data flow.

The operands, which take part in the operation to be executed and which do not change frequently, are stored in the local store, which is configured as a small random-access memory, and then read out as they are needed. The local store is nondestructive in a read mode and thus no write back is required. Successive operands are read out into a single hardware working register and hence, the particular hardware working register is time shared between multiple operands. As far as algorithm execution is concerned, it appears as though the successive operands read from the local store are contained in additional hardware working registers directly accessible for algorithm execution.

Extending the above function further, the local store is also capable of loading not just one hardware working register but all the hardware working registers in the data flow. It is then possible to read out an operand from the local store and retain it in one working register for a period of time, during which other successive operands are read out into the other hardware working registers one at a time.

In addition, a path is provided from at least one of the working registers or its equivalent (such as the ALU output), to permit loading and updating of the operands in the local store.

One specific implementation is illustrated in the figure. A small random- access memory LOCAL STORE has an input bus 1 for data from register Q, and an output bus 2 capable of loading registers A, Q, and B individually. Successive operands are loaded one at a time into each of the working registers A, Q, and B. Under an appropriate control, local store operands are also loadable into any two or all three of the registers simultaneously. Local store is initially loaded from register Q and those operands that must be updated in local store are also rewritten from register Q. Local store addressing is a function of the controls...