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Integrated Complementary Field Effect and Bipolar Transistor Process

IP.com Disclosure Number: IPCOM000081456D
Original Publication Date: 1974-Jun-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Barson, F: AUTHOR

Abstract

In fabricating complementary metal-oxide semiconductor field-effect transistors (MOSFET) and bipolar transistors on the same chip, a P+ region must be formed for the N channel FET and a subcollector region must be formed under the bipolar transistor. The standard technique is to deposit an epitaxial layer and out-diffuse from the substrate, both the P+ pocket and the N+ subcollector simultaneously. However, the subcollector tends to out-diffuse too closely to the emitter and base of the bipolar transistor.

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Integrated Complementary Field Effect and Bipolar Transistor Process

In fabricating complementary metal-oxide semiconductor field-effect transistors (MOSFET) and bipolar transistors on the same chip, a P+ region must be formed for the N channel FET and a subcollector region must be formed under the bipolar transistor. The standard technique is to deposit an epitaxial layer and out-diffuse from the substrate, both the P+ pocket and the N+ subcollector simultaneously. However, the subcollector tends to out-diffuse too closely to the emitter and base of the bipolar transistor.

The present technique utilizes two epitaxial layers, the N+ subcollector being out-diffused from the P- substrate through a P-type epitaxial layer into an N-type epitaxial layer. The P pocket, on the other hand, is out-diffused only from the P- type epitaxial layer into the N-type epitaxial layer.

As shown in the figure, N+ subcollector 7 is diffused into P-substrate 2. A first epitaxial layer 4 is then grown prior to making the P+ pocket diffusion 8. A second epitaxial layer 6 is then grown, followed by a heat cycle for out-diffusing P+ pocket 8 to the wafer surface. The N+ subcollector 7, however, is buried more deeply in the chip. By varying the thickness of epitaxial layer 4, the tail of the out-diffusion 7 may be kept well below the final wafer surface as well as below the collector junction of the NPN bipolar transistor.

It will be recognized that the conductivity types in the figure cou...