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Field Effect Transistor Gate Annealing to Reduce Fixed Charge

IP.com Disclosure Number: IPCOM000081473D
Original Publication Date: 1974-Jun-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Gardner, JA: AUTHOR

Abstract

Silicon dioxide, prepared by thermal oxidation of silicon in a wet oxygen environment has positive charges associated therewith which are temperature dependent. These charges when present in a gate dielectric layer result in threshold instability. The charges in an SiO(2) layer resulting from an oxidation can be reduced to a value approximately that of a layer of SiO(2) formed in dry oxygen at 1200 degrees C, by subsequently annealing the structure in dry, high-purity nitrogen. However, high-temperature nitrogen anneals have a tendency to degrade the oxide breakdown characteristics.

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Field Effect Transistor Gate Annealing to Reduce Fixed Charge

Silicon dioxide, prepared by thermal oxidation of silicon in a wet oxygen environment has positive charges associated therewith which are temperature dependent. These charges when present in a gate dielectric layer result in threshold instability. The charges in an SiO(2) layer resulting from an oxidation can be reduced to a value approximately that of a layer of SiO(2) formed in dry oxygen at 1200 degrees C, by subsequently annealing the structure in dry, high- purity nitrogen. However, high-temperature nitrogen anneals have a tendency to degrade the oxide breakdown characteristics.

In this process, the gate thermal oxide is annealed in an oxygen-nitrogen environment at high temperatures, on the order of 900 degrees C for a time on the order of several hours. The oxygen is preferably present in an amount in the range of 5 to 20%, by volume. This anneal reduces the charge level without degrading the dielectric layer.

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