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High Speed Accumulator

IP.com Disclosure Number: IPCOM000081474D
Original Publication Date: 1974-Jun-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Beraud, JP: AUTHOR [+2]

Abstract

This is a high-speed accumulator for minimizing the carry delay time, by using three input full adders and a judicious arrangement for carry propagation.

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High Speed Accumulator

This is a high-speed accumulator for minimizing the carry delay time, by using three input full adders and a judicious arrangement for carry propagation.

Assuming that binary words A, B, C and D, the bits of which are, respectively, a(n), ..., a(2), a(1), a(o); b(n), ..., b(2), b(1), b(o); c(n), ..., c(2), c(1), c(o); and d(n),
..., d(2), d(1), d(o), are to be accumulated, the procedure is as represented in the figure.

The bits of A and B are fed into a first accumulator stage comprising (n+1) two-input full adders sigma/1/(o) through sigma/1/(n). For the other accumulator stages, each full adder provides a sum bit S and a carry bit K which are fed into three-input full adders, except for the lowest order hit.

The second accumulator stage is made of one two-input full adder sigma/2/(o) and n three-input full-adders sigma/2/(o). The sum bit S/1/(o) provided by sigma/1/(o) is fed into sigma/2/(o), while the carry bit K(o) provided by sigma/1/(o) is fed into sigma/2/(1) together with sum bit S/1/(1) from sigma/1/(1) and bit c(1), and so on.

Similar operations are repeated when the third accumulator stage comprising sigma/3/(o) through sigma/3/(n). Finally, an output stage comprising sigma/4/(1) through sigma/4/(n) provided the overall accumulation result, the bits of which are S/4/(n), ..., S/4/(2), S/4/(1) and S/3/(o).

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