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Multiple Selection Detection and Encoding Circuit

IP.com Disclosure Number: IPCOM000081475D
Original Publication Date: 1974-Jun-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Benichou, C: AUTHOR [+3]

Abstract

This circuit combines the function of an encoder with a multiple selection detection. A typical application is the match address coding of an associative array with a multiple match detection as an error mode.

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Multiple Selection Detection and Encoding Circuit

This circuit combines the function of an encoder with a multiple selection detection. A typical application is the match address coding of an associative array with a multiple match detection as an error mode.

A typical arrangement is shown in the figure, where the array is composed of 2/n/ word lines W1 to WN (N = 2/n/) and n bit line pairs B1 to Bn. Each bit line pair has two bit lines R and L.

The coding function is performed by cells which connect every word line to every bit line pair following a predetermined coding configuration. The cell is connected to bit line R when the address bit is 1 and to bit line L when the address bit is 0.

When a word line is selected, all the bit lines connected to this word line through a cell T, have their levels changed. In operation, the L and R levels are identical.

Array cells T are ORed along the bit lines. If only one word line has been selected, L and R for each bit assume complementary states R = L. The coded output R1, R2 .... Rn-1, Rn is available.

If two word lines have been selected simultaneously, the two addresses corresponding to these two word lines will be different at least on one bit, and the corresponding bit line pair will have the same state on its R and L lines. By comparing the identity of R and L lines on every bit pair and ORing the results, the simultaneous addressing will be detected by comparison circuits C since at least one bit line pair will ha...