Browse Prior Art Database

Gas Panel Decoder/Driver

IP.com Disclosure Number: IPCOM000081485D
Original Publication Date: 1974-Jun-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Liang, RN: AUTHOR

Abstract

This gas panel decoder/driver circuit functions as a high-voltage, single-pole double-throw switch with memory. A plurality of the decoder/ driver circuits may be integrated, each driving line of a gas panel requiring two decoder/driver circuits which function in complementary fashion by appropriate logic. The memory feature of the decoder/driver is necessary for the unique operation of the gas panel. The memory is operated in a different way instead of standard flip-flop gates. This feature reduces power dissipation and reduces chip size.

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Gas Panel Decoder/Driver

This gas panel decoder/driver circuit functions as a high-voltage, single-pole double-throw switch with memory. A plurality of the decoder/ driver circuits may be integrated, each driving line of a gas panel requiring two decoder/driver circuits which function in complementary fashion by appropriate logic. The memory feature of the decoder/driver is necessary for the unique operation of the gas panel. The memory is operated in a different way instead of standard flip- flop gates. This feature reduces power dissipation and reduces chip size.

Fig. 1 shows a plurality of the decoder/driver circuits 10 and 11 connected to the "X" and "Y" axis of a gas panel array 12. Each switch 10 and 11 is connected between VH and VL for Y decoder/driver and HH and HL for the X decoder/driver.

Figs. 2 and 3 show the X and Y decoder/drivers 10 and 11, respectively. Decoder input 13' selects one driver and "latch off" for X driver and decoder input 13'' selects one driver and "latch on" for Y driver. Set line 12 turns on all of the switches at the same time for a positive going pulse. Reset line 14 turns off all of switches at the same time.

When Q1 is on, Q2 and Q3 are off. When Q2 and Q3 are on, Q1 is off. Furthermore, when Q2 and Q3 are pn, they stay on by latching current from Va due to positive feedback from Q2 and Q3. The positive feedback current provides the circuit with "memory". Q4 is part of a decoder and part of the feedback circuit to minimize th...