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Browse Prior Art Database

FET N Channel Threshold Voltage Control Circuit

IP.com Disclosure Number: IPCOM000081487D
Original Publication Date: 1974-Jun-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Chang, HC: AUTHOR

Abstract

Substrate bias voltage is controlled within a very narrow range to compensate for process variation in N-channel device fabrication.

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FET N Channel Threshold Voltage Control Circuit

Substrate bias voltage is controlled within a very narrow range to compensate for process variation in N-channel device fabrication.

The terminal E1 and node NS are connected to the gate electrode and substrate electrode, respectively, of a field-effect transistor (FET) device, not shown, for control of its threshold voltage. Devices A and B establish a reference for the threshold voltage. This voltage is primarily determined by the size of devices A and B and secondarily by the power supply and threshold voltage. NA is chosen to be about a half a volt above the desired threshold voltage of a grounded source device. Devices C and D form a conventional amplifier to provide a voltage at node NB that controls the gate electrode of device E.

As the threshold voltage increases, node NB is increased to further bias device E more positively. As device E turns on harder, device G is turned on harder to increase the substrate voltage at node NS. Device F which is normally off is turned on, to lower the potential difference between E1 and NS. In effect device G and resistor R act as a voltage device that is controlled relative to a reference voltage determined at node NA. Node NS is made less negative as the threshold voltage increases. When the threshold voltage is below the reference level, the substrate bias is made more negative.

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