Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Asynchronous Frequency Monitor/Analyzer

IP.com Disclosure Number: IPCOM000081488D
Original Publication Date: 1974-Jun-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 85K

Publishing Venue

IBM

Related People

Blackmore, SR: AUTHOR

Abstract

This circuit monitors the frequency of any given signal and generates a "fault" signal if the monitor signal (TMS) is outside a given tolerance range. The circuit will also indicate when the TMS frequency is high or low or absent.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 2

Asynchronous Frequency Monitor/Analyzer

This circuit monitors the frequency of any given signal and generates a "fault" signal if the monitor signal (TMS) is outside a given tolerance range. The circuit will also indicate when the TMS frequency is high or low or absent.

Frequent monitoring is initiated by the setting of a flip-flop 10 designated INIT.FF. A gated 1K hertz signal 20 is provided as a first input. A power-on reset (POR) signal 13 is provided as a second input through NOR gate 14 and amplifier 16. A tie-up signal 18 provides the remaining input to the flip-flop 10. The output from flip-flop 10 appears as node J in the timing charts shown in Fig.
2.

A four-bit binary counter 22 receives a output from flip-flop 10 as one input.

A frequency to be monitored (TMS) signal 24 is provided as a second input to the counter 22. A signal 12 is also provided as another input to the counter 22. The signal 12 is provided through NOR gate 26 and amplifier 28. The output from amplifier 28 appears as node G in the timing chart of Fig. 2.

The counter 22 monitors the frequency by observing each positive transition of the signal 24. A positive transition causes the counter 22 to increment by one. Upon receiving a gate signal 20, and the counter is between 8 and 12, the monitored frequency is within the frequency range. In this condition, low flip-flop (LONOTFF) 30 and a flip-flop (HIFF) 32 provide the same output level as shown at nodes C and D in Fig. 2.

When the gate si...