Browse Prior Art Database

Online Minimum Probing LSI Testing System

IP.com Disclosure Number: IPCOM000081494D
Original Publication Date: 1974-Jun-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 32K

Publishing Venue

IBM

Related People

Chao, CC: AUTHOR [+2]

Abstract

This data compression technique for a large-scale integrated (LSI) testing system uses error detecting/correcting codes.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

Online Minimum Probing LSI Testing System

This data compression technique for a large-scale integrated (LSI) testing system uses error detecting/correcting codes.

It involves mapping the expected output responses for each input test pattern into the check bits of a predetermined error detecting code. If the number of output lines is k and the number of checks bits is r, then the compression ratio is k/r which implies the saving in probings and probes, as well as the required storage (memory) for the output patterns in the tester. Furthermore, for r check bits used, an error detecting capability is obtained using this technique greater or equal to (1 1 over 2r) x 100%.

On a logic wafer, each primary output may be treated as equivalent to a "bit" for the error detection circuit--logic one as bit "1", logic zero as bit "0". A built-in error detection circuit is used to compress all the wafer's primary outputs per test pattern.

The error detection circuits basically contains a parity generator--to generate a parity "bit" based on all the wafer's primary outputs physically present at the wafer, in response to an input parity bit with the software predicted parity bit. In case of a mismatch, an error signal shows up.

The predicted parity bit with the corresponding input test pattern may be directly fed into a wafer's primary inputs, each time a test pattern is applied. As an alternative, the predicted parity bit corresponding to each test pattern number may be prestored in the tester's memory and the parity comparison may be done in the tester.

A primary wafer output may be used either for the output of the pa...