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Solid State Power Sequencing System

IP.com Disclosure Number: IPCOM000081503D
Original Publication Date: 1974-Jun-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 4 page(s) / 123K

Publishing Venue

IBM

Related People

Bodner, RE: AUTHOR [+3]

Abstract

This solid-state power sequencing system utilizes triggers controlled by logic circuitry, which ensures that multiple power supplies are powered up and down in a predetermined sequence. Such an arrangement protects circuit components in the utilization devices during the power up sequence, because certain voltages are made available before other voltages which if present first would cause catastrophic damage. Similarly, during the power-down sequence, certain voltages are removed first so as to prevent irreversible damage to electronic components.

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Solid State Power Sequencing System

This solid-state power sequencing system utilizes triggers controlled by logic circuitry, which ensures that multiple power supplies are powered up and down in a predetermined sequence. Such an arrangement protects circuit components in the utilization devices during the power up sequence, because certain voltages are made available before other voltages which if present first would cause catastrophic damage. Similarly, during the power-down sequence, certain voltages are removed first so as to prevent irreversible damage to electronic components.

Power supplies 10, 20 and 30, Fig. 1, are powered up and down in a predetermined sequence under control of sequence control circuit 40. Each power supply or sense circuitry associated therewith provides error signals indicative of no voltage, undervoltage, overvoltage and overcurrent. The power- up sequence is initiated by a start pulse which is usually furnished by manually operating a start switch, the start switch being connected to a single-shot multivibrator 45, Fig. 2. The start pulse will set sequence trigger 46, provided thermal sense latch 47 is not set. Thermal sense latch 47 is set by a thermal sense signal coming from any thermal sense detector within the devices, which are powered by the power supplies 10, 20 and 30. Obviously if there is a thermal sense condition, none of the power supplies should be powered up.

The output of trigger 46 is applied to power supply 10 as a start signal. Power supply 10 can be powered up even though initially there will be an undervoltage (UV) error signal from this power supply. This is because the start pulse provides an inhibit undervoltage power supply 10 signal via OR circuit 48. Once power supply 10 comes up to its operating voltage, power supply 20 can be started. Of course, there will be an error signal present indicating that power supply 20 is undervoltage. This does not prevent power supply 20 from being started, because there will be an inhibit undervoltage 20 signal preventing an UV error in response to the start pulse via OR circuit 52. Further, OR circuit 55 and inverter 56 provide a signal for clocking sequence trigger 51 on. The output of sequence trigger 51 provides a start signal for starting power supply 20. OR circuit 65 and inverter 66 function to provide a signal indicative when voltage supply 20 is not undervoltage. Thus the output of inverter 66 provides a signal for clocking sequence trigger 61 on. OR circuit 62 provides an inhibit undervoltage power supply 30 signal, to enable power supply 30 to be started by the output signal from trigger 61.

When single-shot multivibrator 45 times out as seen in the timing diagram of Fig. 3, the inhibit undervoltage signals for power supplies 10, 20 and 30 drop to a down level enabling detection of undervoltage conditions.

An any error signal indicative of any error in any of the power supplies 10, 20 or 30 sets any error lat...