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Clock Phase Correction for Digital Data Recording

IP.com Disclosure Number: IPCOM000081517D
Original Publication Date: 1974-Jun-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 57K

Publishing Venue

IBM

Related People

Ho, JP: AUTHOR [+2]

Abstract

In conventional phase-locked data-recording circuits using FM recording, clock pulses from the incoming data are compared to a reference oscillator operating at the data frequency. Phase errors produce a correction voltage for altering the frequency of the oscillator. But, for modified frequency-modulation (MFM) recording, the clock pulses do not occur at regular intervals. Corrections must then be produced from both the clock pulses and the data pulses. Since pulses may be entirely absent during any bit time, it is necessary to determine whether a pulse does occur, to remember how early or late the pulse is, and to perform the appropriate correction during the following bit time.

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Clock Phase Correction for Digital Data Recording

In conventional phase-locked data-recording circuits using FM recording, clock pulses from the incoming data are compared to a reference oscillator operating at the data frequency. Phase errors produce a correction voltage for altering the frequency of the oscillator. But, for modified frequency-modulation (MFM) recording, the clock pulses do not occur at regular intervals. Corrections must then be produced from both the clock pulses and the data pulses. Since pulses may be entirely absent during any bit time, it is necessary to determine whether a pulse does occur, to remember how early or late the pulse is, and to perform the appropriate correction during the following bit time.

Circuit 10, Fig. 1, employs a high-frequency voltage-controlled oscillator (VCO) 11 and digital counting to perform these functions, while avoiding the drift and accuracy problems associated with analog circuits. VCO 11 operates at 32 times the data rate. Counter 12 divides the VCO frequency by 32, to produce the WINDOW pulses shown in Figs. 2 and 3. Output X1 of counter 12 produces the X1 OUT pulses at twice the frequency of the WINDOW pulses, as shown on the second line of Figs. 2 and 3.

The DATA pulses of Figs. 2 and 3 set latch 13, Fig. 1. This latch is reset when decoder 14 detects that divide-by-16 counter 15 has reached a predetermined count. Counter 15 is advanced by AND gate 16 synchronously with VCO 11 whenever latch 13 is set.

Phase discriminator 17 receives both the X1 OUT signal and the output of latch 13, X2 OUT. Fig. 2 shows the relationship of the DATA and X2 OUT pulses when the incoming digital data is arriving early with respect to its proper position, line 20, at the middle...