Browse Prior Art Database

Pinhole Detection in Oxide Layers on Integrated Circuits

IP.com Disclosure Number: IPCOM000081532D
Original Publication Date: 1974-Jun-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Chase, BD: AUTHOR

Abstract

A significant cause for failure of integrated circuits is the presence of pinholes in the oxide layer over the semiconductor material. These pinholes can be detected using a scanning electron microscope (SEM), in which the beam is arranged to scan the surface of the semiconductor wafer. This technique will be described with reference to an integrated circuit containing an array of field-effect transistors (FET's), although it can also be used for detecting pinholes in integrated circuits containing bipolar transistors.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Page 1 of 2

Pinhole Detection in Oxide Layers on Integrated Circuits

A significant cause for failure of integrated circuits is the presence of pinholes in the oxide layer over the semiconductor material. These pinholes can be detected using a scanning electron microscope (SEM), in which the beam is arranged to scan the surface of the semiconductor wafer. This technique will be described with reference to an integrated circuit containing an array of field-effect transistors (FET's), although it can also be used for detecting pinholes in integrated circuits containing bipolar transistors.

In the drawing, a semiconductor wafer consists of a substrate 1 of P conductivity type semiconductor material having formed therein N conductivity type source and drain regions 2 and 3, respectively. Source and drain contacts 4 and 5 make contact with source and drain regions 2 and 3. Covering the surface of the semiconductor wafer is an insulating layer 6 of insulating material. (In practice, of course, layer 6 will be a composite structure mainly of oxide but possibly including nitride.) Embedded within insulating layer 6 are gate electrodes 7.

In operation, the semiconductor wafer 3 is placed within the SEM and electrical connections are made from commonly connected source and drain contacts 4 and 5 and substrate 1 to current amplifier 8. Preferably substrate 1 is grounded as shown. The beam voltage of the electron beam is adjusted so that electrons in the electron beam 9 will penetrate la...