Browse Prior Art Database

Nonvolatile Diode Cross Point Memory Array

IP.com Disclosure Number: IPCOM000081586D
Original Publication Date: 1974-Jul-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Arnett, PC: AUTHOR [+2]

Abstract

This is a dense memory array in which every cross-point of two insulated orthogonal sets of lines defines a nonvolatile memory device, which utilizes voltage and storage charge to control breakdown characteristics of a PN junction.

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Nonvolatile Diode Cross Point Memory Array

This is a dense memory array in which every cross-point of two insulated orthogonal sets of lines defines a nonvolatile memory device, which utilizes voltage and storage charge to control breakdown characteristics of a PN junction.

Basically, the array comprises parallel insulated metallic word lines 26 orthogonal to bit lines 14, 16, 18 and 20 diffused in a semiconductor body 11. Each crossing of each metal word line 26 over a diffused bit line 14, 16, 18 and 20, defines a separate and distinct memory cell. Insulation layers 22, 24, between the word lines and the bit lines have dual-charge states and can store charges.

Biasing of the word and bit lines causes charges to be injected into insulation 22, 24 to affect the surface field of the body, and thus change the breakdown voltage of the diffusions with respect to the semiconductor body 11. Both the read and write operations involve voltage breakdown of PN junctions 15, 17, 19 and 21 between diffused bit lines 14, 16, 18 and 20 and the body 11, respectively.

During the write operation, an avalanche breakdown of the junctions is caused to occur and charge carriers are injected into overlying insulation 22, 24. Charge carriers 56 so injected remain localized in insulation layers immediately above the junctions and, therefore, do not disturb the information on adjacent bit lines.

To erase, a voltage is applied to cause the injected carriers to be driven out of insulation...