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Error Checking and Correction of Microprogram Control Words With a Late Branch Field

IP.com Disclosure Number: IPCOM000081591D
Original Publication Date: 1974-Jul-01
Included in the Prior Art Database: 2005-Feb-28

Publishing Venue

IBM

Related People

Healey, RA: AUTHOR

Abstract

Symmetrical error checking and correction (ECC) codes permit selection (by late branch address bits) without delay of one of N control words read simultaneously from control store with their ECC bits. Microprogram control stores which are implemented by semiconductor storage cells, are usually provided with SEC (single-error correction) - DED (double-error detection) circuits to assure system availability and error-free operation,. Many systems in use today access two or more control words simultaneously from the control store; and one of these control words is selected by late branch circuits for use as the next control word, based upon the late branch information.

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Error Checking and Correction of Microprogram Control Words With a Late Branch Field

Symmetrical error checking and correction (ECC) codes permit selection (by late branch address bits) without delay of one of N control words read simultaneously from control store with their ECC bits. Microprogram control stores which are implemented by semiconductor storage cells, are usually provided with SEC (single-error correction) - DED (double-error detection) circuits to assure system availability and error-free operation,. Many systems in use today access two or more control words simultaneously from the control store; and one of these control words is selected by late branch circuits for use as the next control word, based upon the late branch information.

Typically the ECC circuits are coupled directly to the output of the control store, but no check is made at the output of the control register to which the selected next control word is gated. Thus even though data read from the control store may be error free, nevertheless the output of the control store may contain an error. It is, therefore, desirable to have the ECC circuitry coupled to the output of the control register.

In control store applications utilizing ECC circuits, it is desirable to have the ECC check bits generated across all data bits being read out. In general, this method saves storage bits. For example, when two 32-bit control words are read out, only eight check bits are required across all 64 data bits. However, in the event that each 32-bit control word of a double-control word is separately checked, seven check bits are required for each word. Thus three check bits per control word can be saved in the control store if ECC checking is across all 64 data bits read out.

ECC checking of the output of the control register rather than the control store gives rise to speed and circuit complexity problems. In one application, the control register is duplicated so that both control words read from control store are gated by the branching circuits into the two control registers. However, only one of the two control registers is used for controlling the processor, and the other control register holds the nonselected word and provides an input (together with the primary control register) to the ECC circuits.

In order that the ECC circuits correctly function, the control words must be reassembled into the exact control store relation before being presented to the ECC check circuit. This is illustrated in Fig. 1 by gating circuits 1 which are controlled by the branch information input at 2, to reassemble words in control registers 3 and 4 for ECC circuits 5. Logic circuits 6 gate the control words from control store 7 to registers 3 and 4 in response to branch information at input 2.

A procedure is described below which eliminates the need for the reassembly circuits 1 and their inherent logic delays, i.e., registers 3 and 4 are connected directly to ECC circuits 5. The proc...