Browse Prior Art Database

Current Multiplier

IP.com Disclosure Number: IPCOM000081593D
Original Publication Date: 1974-Jul-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Radcliffe, JK: AUTHOR

Abstract

In a computer power distribution test system, fast rise times are maintained while current multiplication is achieved.

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Current Multiplier

In a computer power distribution test system, fast rise times are maintained while current multiplication is achieved.

Feed line 1 has a characteristic impedance Z(01) chosen to match that of feed generator FG. Load line 2 has a characteristic impedance Z(02) much lower than Z(01) and is used to feed load L. Lines 1, 2 constitute transmission lines interconnected as shown at A, B and C, providing a series of feed line segments and load line segments each arranged in pairs having the same time delays, though each pair need not have the same delay as another pair.

As the incident current I(1) moves down feed line I, it divides at A and is injected into load line 2 as well as continuing down line 1. In view of the matched time delays, the signals arrive at the same time at junction B, where half the current from the feed line is added to load line 2. At last junction C the full feed current is added to the load line 2. For greater multiplication more B-type junctions may be added.

This arrangement provides a theoretical current multiplication factor of 2 + n/2 (where n is the number of B-type junctions); however in practice, the impedances used will result in a somewhat less available current. The current pulse will remain up for a period equal to twice the time delay in the shortest line segment, until reflections begin to degrade the amplitude. Current doubling at the load may also be achieved if the load being driven has a low impedance in rela...