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Dual Diode Logic Gate and Oscillation Clamping Structure

IP.com Disclosure Number: IPCOM000081625D
Original Publication Date: 1974-Jul-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Gani, VL: AUTHOR [+2]

Abstract

Figs. 1 and 2 depict the structure of a semiconductor device, the circuit thereof being schematically shown in Fig. 3. Fig. 1 is a top view. Fig. 2 is a sectional view taken along the lines 2-2 of Fig. 1.

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Dual Diode Logic Gate and Oscillation Clamping Structure

Figs. 1 and 2 depict the structure of a semiconductor device, the circuit thereof being schematically shown in Fig. 3. Fig. 1 is a top view. Fig. 2 is a sectional view taken along the lines 2-2 of Fig. 1.

Using a minimum of additional silicon area (Fig. 1) oscillation damping diodes D2 may be added at the inputs of the logic gate, Fig. 3.

By adding a strip of metallurgy S to the logic gate D1 structure, diode D2 is formed to effectively clamp oscillations at the input of the logic gate. Multiple clamp diodes may be fabricated with the same metal strip, as all D2 anodes are electrically common.

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