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Modified DTL Internal Logic Circuit

IP.com Disclosure Number: IPCOM000081629D
Original Publication Date: 1974-Jul-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Gruodis, AJ: AUTHOR [+2]

Abstract

The circuit shown in the figure performs the AND-Invert (AI) logic function. Circuit performance is enhanced over the conventional diode-transistor logic (DTL) circuit by a factor of 2.5 or greater for the same power level, while using only one positive power supply ( >/- 2.5V,)and ground. Speed improvement is accomplished by use of the modified Darlington configuration consisting of transistors T1 and T2, which are never allowed to enter classic "deep" saturation and the fact that T1 never really shuts off.

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Modified DTL Internal Logic Circuit

The circuit shown in the figure performs the AND-Invert (AI) logic function. Circuit performance is enhanced over the conventional diode-transistor logic (DTL) circuit by a factor of 2.5 or greater for the same power level, while using only one positive power supply ( >/- 2.5V,)and ground. Speed improvement is accomplished by use of the modified Darlington configuration consisting of transistors T1 and T2, which are never allowed to enter classic "deep" saturation and the fact that T1 never really shuts off.

The power dissipation level of the circuit is minimized, since the Darlington configuration allows the design of a very small base current into T1 to support the collector-resistor load current IR3, and the fan out load current at node 2.

Logically, inputs A, B, and C must be at an "up" or "1" level for transistors T1 and T2 to be in the "on" state. With all three inputs at a 1 level, the input Schottky diodes D1, D2 and D3 tend to become reverse biased and stop conducting. Current from +Vsup is then supplied through the base current limiting resistor R1 into the base of T1, thus causing T1 to conduct to its on state. The emitter current of T1, IE1, supplies current to the pulldown resistor R2 and into the base of transistor T2 thus turning T2 on.

With both T1 and T2 conducting, a current IR3 flows through resistor R3 forcing the voltage at node 1 to a potential equal to (VBE1 + VBE2 - VD4) and the voltage at the output nod...