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Digital Data Detector Circuit

IP.com Disclosure Number: IPCOM000081651D
Original Publication Date: 1974-Jul-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Fiorino, BC: AUTHOR [+2]

Abstract

This circuit is capable of detecting, by using integration techniques, data from readback signals that are obtained from magnetic record carriers employing, for example, the NRZI data representation scheme. As data increase, the time available for data detection and squelching decreases. For this reason, it is advantageous to use alternate cycle integration which is also applicable to phase-error detection or phase-shift measurement. The detector circuit employs the alternately cycled squelch reference as a source for phase-shift measurement reference signals.

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Digital Data Detector Circuit

This circuit is capable of detecting, by using integration techniques, data from readback signals that are obtained from magnetic record carriers employing, for example, the NRZI data representation scheme. As data increase, the time available for data detection and squelching decreases. For this reason, it is advantageous to use alternate cycle integration which is also applicable to phase-error detection or phase-shift measurement. The detector circuit employs the alternately cycled squelch reference as a source for phase- shift measurement reference signals.

Magnetic record sensing circuits generate +D and -D input data signals of opposite polarity. These signals are applied to inputs 10, 11 of the detector circuit, and are also used to synchronize a variable-frequency timer which generates clock pulses +C, -C, 2C to be applied to inputs 12, 13, 14 and 15, respectively. The D signals are supplied to both the first and the second ACI (Alternately cycled Integrators) 16 17 operating as synchronous demodulators, which are alternately and successively actuated by +C and -C clock pulses. ACI's 16, 17 are identically constructed, as are the squelch circuits 18, 19.

ACI 16 integrates data negatively whenever -C pulses are active. Squelch circuit 18 squelches integration capacitors 20, 21 in a capacitive emitter-follower circuit configuration. Rapid integration and differentially balanced squelching is provided for both capacitors. The H-configured integration circuit includes a pair of squelch transistors 22, 23 forming two legs of the H, with a pair of integrating switch transistors 24, 25 forming the other two legs. Capacitors 20, 21 form th...