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An FET 4-Phase Dynamic Off Chip Driver With Polarity Hold

IP.com Disclosure Number: IPCOM000081657D
Original Publication Date: 1974-Jul-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Cox, DT: AUTHOR [+4]

Abstract

The field-effect transistor (FET) 4-phase dynamic logic off-chip driver with polarity hold of Fig. 1 samples the output of array 10 at dynamic logic phase 3 times, shown in Fig. 2, to charge or discharge node capacitance 11 which retains its charge for a full dynamic logic cycle, allowing output FET 13 to provide a static output on or off signal to a TTL logic circuit. Array precharge FET 15 is rendered conductive during phase 2, charging array node capacitance 17. Precharge FET 21 also charges thin oxide capacitance 23 through FET 25 to phase 4 line driver at phase 2 time, when phase 4 is at zero volts.

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An FET 4-Phase Dynamic Off Chip Driver With Polarity Hold

The field-effect transistor (FET) 4-phase dynamic logic off-chip driver with polarity hold of Fig. 1 samples the output of array 10 at dynamic logic phase 3 times, shown in Fig. 2, to charge or discharge node capacitance 11 which retains its charge for a full dynamic logic cycle, allowing output FET 13 to provide a static output on or off signal to a TTL logic circuit. Array precharge FET 15 is rendered conductive during phase 2, charging array node capacitance 17. Precharge FET 21 also charges thin oxide capacitance 23 through FET 25 to phase 4 line driver at phase 2 time, when phase 4 is at zero volts.

If any of array FET's 19 are rendered conductive at phase 3 time, thin oxide capacitor 23 will be discharged by the conductive FET 19 through FET devices 25 and 29, because phase 4 line is still at zero volts during phase 3 time. As capacitances 17 and 23 are discharged, FET 31 is held off allowing FET 33 to turn FET 35 on, thereby discharging node capacitance 11. Capacitance 11 being discharged turns off FET output transistor 13 allowing off-chip resistor 39 to begin charging off-chip capacitor 41, so that a valid up-level output signal will be available at the beginning of phase 1 time.

Capacitor 23, having been discharged durinX phase 3 time, prevents FET device's 25, 43 and 45 from conducting during phase 4 time when phase 4 line rises to 8.5 volts. FET device 47 is conductive during phase 4 time to keep FET 35 conducting, thereby ensuring tha...