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Logic Card Comparison Analysis Tester

IP.com Disclosure Number: IPCOM000081665D
Original Publication Date: 1974-Jul-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 60K

Publishing Venue

IBM

Related People

Baker, GO: AUTHOR [+5]

Abstract

The tester control switches 10 are preset according to the card under test. The logic for each part number card to be tested is reviewed to determine which input/output (I/O) pins are "inputs" or "outputs".

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Logic Card Comparison Analysis Tester

The tester control switches 10 are preset according to the card under test. The logic for each part number card to be tested is reviewed to determine which input/output (I/O) pins are "inputs" or "outputs".

The 104 I/O "Pin Select" switches 12 select the desired logic function for each I/O pin at the test socket. The switches provide the following functions:
Random Data - Allows the output of the Random Pulse Generator 14 to provide random data patterns to the card I/O

pin.

Standard - Force inputs (+)1. With the switch in this position, all selected test socket I/O pins

will be held to a constant "1" or (+) polarity.

Output - With the switch in this position, the tester output drivers are held "off" or to a "0" (-) polarity.

This is used when the card under test provides an

output pulse which must be detected and compared

for error against a "Standard Card".

The Random Pulse Generator 14 combines two different frequencies in an "exclusive OR" circuit; the output, when selected, provides random data patterns to the Data Pattern Store Latch 16. There are 104 Random Pulse Generators, each with different "mixed" oscillator frequencies. The tester Clock 18 is fed by a high-frequency oscillator 20 that is stepped through a series of countdown binary counters. The tester Frequency Control Switch 22 selects three outputs from these counters to provide a tester cycle time of 250 ns or 1 Mu sec or 2 Mu sec. The clock output is one line of continuous symmetrical pulses of one of the above cycle times.

The tester sequence of events is primarily the function of four interrelated circuits; the 105-bit counter/decoder 24, the Data Pattern Store Latch 16, the Data Latch 26, and the 133-bit memory 28.

The 105-bit counter/decoder 24 provides a separate sequential timing pulse to each of the 104 Data Latches 26 and to the Special Driver Card 30. The last step of the counter/decoder 24 sets the 104 Data Pattern Store Latches 16, all at the same time, to the data from OR 32 at the inputs to these latches.

The outputs of the 104 Data Pattern Store Latches 16 are set sequentially into the 104 Data Latches 26. The outputs of the 104 Data Latches provide the data patterns seen at the test socket I/O pins 39 selected as input...