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Automatic Thresholding and Shading Circuit for Solid State Cameras and Scanners

IP.com Disclosure Number: IPCOM000081682D
Original Publication Date: 1974-Jul-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Nelson, RG: AUTHOR

Abstract

This circuit arrangement is designed for quantinizing video inform information from a scanning array, and overcoming any non-uniformity in lighting of the subject and non-uniformity in photodiode sensitivity.

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Automatic Thresholding and Shading Circuit for Solid State Cameras and Scanners

This circuit arrangement is designed for quantinizing video inform information from a scanning array, and overcoming any non-uniformity in lighting of the subject and non-uniformity in photodiode sensitivity.

A video signal is applied at terminals 10, 11 to an amplifying circuit 12 with series resistor 14 interposed for isolating the amplifier 12 to some extent. The amplifier 12, a capacitor 16, a resistor 18 and a field-effect transistor (FET) 20 form a sample-and-hold circuit. The output of this circuit is fed back to the amplifier 12 through a parallel resistor 22 and capacitor 24 combination.

The sample-and-hold circuit is gated at the rate of the video signal transitions applied at terminals 26, 28, just slightly delayed by two cascaded monostable flip-flop circuits 30, 32.

A comparator circuit comprising two differential amplifying circuits 36, 38 is gated just slightly ahead of the sample-and-hold circuit, by a connection to the first monostable flip-flop circuit 30 only. A black-to-white signal is taken from the input terminals 10, 11 and applied to the amplifier 36 by way of a level setting potentiometer 42, and similarly a white-to-black signal is applied to the amplifying circuit 38 by way of another level setting potentiometer 44. The output level from the FET 20 is applied in common to the amplifiers 36 and 38 to complete the comparator circuit.

A pair of analog gating ci...